This application claims the priority benefit of Taiwan application serial no. 91 105278, filed on Mar. 20, 2002.
1. Field of the Invention
The present invention relates to a method for fabricating a memory device. More particularly, the present invention relates to a method for fabricating a read only memory device.
2. Description of Related Art
The read only memory device provides the non-volatile property, wherein the stored information is retained even electrical power is interrupted. As a result, the read only memory device is incorporated into many electronic products to maintain a normal operation for the products. The mask read only memory device is the most fundamental type of read only memory device. A typical mask ROM device uses a channel transistor as the memory device. The programming of a mask ROM device is accomplished by selectively implanting ions to an identified channel region. By altering the threshold voltage, the control of the xe2x80x9conxe2x80x9d state and the xe2x80x9coffxe2x80x9d state of the memory device is thus achieved.
A typical mask read only memory device comprises a polysilicon word line crossing over a bit line. The region under the word line and between the bit lines is the channel region of the memory device. Whether or not ions are implanted to the channel region determines the storage of the binary digit of either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, wherein the implanting of ions to the identified channel region is known as code implantation.
In general, when a code implantation process is performed on a mask read only memory, a patterned photoresist layer that exposes a pre-coding region is formed with a photomask. An ion implantation process is then performed to implant dopants to the pre-coding region in the substrate under the stacked gate structure. Usually, as required by the circuit design, an isolated pattern region and a dense pattern region are formed on a same photomask. An overexposure and an underexposure in the isolated pattern region and in the dense pattern region often occur during the transferring of a mask pattern due to the optical proximity effect. The accuracy of the critical dimension of the transferred pattern is thereby affected. Consequently, a misalignment would result as dopants are being implanted to the identified channel region of a mask read only memory device during the code implantation process. Information that is being stored in the memory cells of the memory device is thus erroneous to adversely affect the operational function of the memory device and the reliability of the products.
Conventionally, to correct the non-uniformity of pattern in the dense pattern region and the isolated pattern region of a coding mask of a mask read only memory device, the optical proximity correction technique is employed to design a mask with a special pattern. However, this type of mask with a special pattern, not only increases the manufacturing time, it also complicates the manufacturing process and increases the manufacturing cost. Further, after the fabrication of the photomask is completed, it is rather difficult to debug the defects in the pattern of this type of photomask.
Accordingly, the present invention provides a fabrication method for a read only memory device, wherein the openings in the dense pattern region and in the isolated patter region in the memory cell array of the mask read only memory device are formed having the same dimension, even without the application of the optical proximity correction technique.
Based on the foregoing reasons, the present invention provides a fabrication method for a read only memory device. The method provides a substrate that comprises a memory cell region and a periphery circuit region, wherein a memory cell array is formed in the memory cell region and a plurality of transistors is formed in the periphery circuit region. A precise layer that comprises a plurality of first openings is then formed on the identical. Further these first openings are located above the channel region of each of the first memory cells in the memory cell array. A mask layer that comprises a plurality of second openings and third openings is formed on the substrate. The aforementioned second openings are positioned above a plurality of the pre-coding memory cell regions in the memory cell region, while the third openings are positioned above the gates of the transistors in the periphery circuit region. An ion implantation process is then conducted to code the memory cells in the pre-coding memory cell region and to adjust the threshold voltage of the transistors.
The present invention employs a precise photomask to pattern a pattern-transferred layer (a precise layer), wherein openings are defined above the channel region of each memory cell and the critical dimension of these openings is identical. Another patterned photoresist layer (mask layer) is then formed on the substrate. The patterned photoresist layer exposes a pre-coding memory cell region in the memory cell region and a gates of the transistors in the periphery circuit region. Thereafter, using the pattern-transferred layer (precise layer) and the patterned photoresist layer (mask layer) as a coding mask for the mask read only memory device, the pre-coding memory cell is coded and the threshold voltage of the transistors is adjusted. According to the present invention, the critical dimension of each of the openings in the precise layer is about the same and each opening is precisely corresponded to the channel region of each memory cell. The problem of having critical dimension difference between the coding windows in the isolated pattern region and that in the dense pattern region due to the optical proximity effect is prevented. Further, when the code implantation is being performed on the pre-coding memory cell in the memory cell region, the threshold voltage of the transistors in the periphery circuit region is concurrently adjusted to further simplify the manufacturing process.
Further, the present invention also employs a photoresist layer as the pattern-transferred layer. When the pattern-transferred layer comprises a photoresist material, a deposition step and an etching step can be omitted to further simplify the manufacturing process and to further reduce the manufacturing cost. Moreover, according to the present invention, deviation in the critical dimension between the dense pattern region and the isolated pattern region is mitigated by using two photoresist layers.
Further, the precise layer in the periphery circuit region can be completely opened or selectively opened or completely not opened. The second opening and the third opening in the mask layer can form with one piece of photomask or two pieces of photomask.
The present invention provides a fabrication method for a read only memory device. This method provides a substrate that comprises a memory cell region and a periphery circuit region, wherein a memory cell array is formed in the memory cell region and a plurality of transistors is formed in the periphery circuit region. A mask layer that comprises a plurality of first openings and second openings is formed on the substrate. The first openings are located above a plurality of pre-coding memory cell regions in the memory cell region and the second openings are located above the gates of the transistors in the periphery circuit region. A precise layer is formed on the memory cell region. The precise layer comprises a plurality of third openings, wherein the critical dimension of each of the third openings is identical and the third openings are positioned above the channel region of the pre-coding memory cell in the pre-coding memory cell region. Thereafter, an ion implantation process is conducted to code the pre-coding memory cells in the pre-coding memory cell region and to adjust the threshold voltage of the transistors, using the mask layer and the precise layer as a coding mask.
Accordingly, the present invention employs a photomask to pattern the pattern-transferred layer, wherein the pre-coding memory cell region in the memory cell region and the gates of the transistors in the periphery circuit region are exposed. Further using the precise photomask, a plurality of openings having the same critical dimension is defined in the memory cell region. Further, these openings are located above the channel regions of the pre-coding memory cell in the pre-coding memory cell regions, exposing the word line of the memory cell. The critical dimension of each opening in the precise layer is identical and each opening in the precise layer precisely corresponds to the channel region of each memory cell. Even without the application of the optical proximity correction technique to manufacture the coding mask, any deviation in the critical dimension of the coding window between the dense pattern region and the isolated pattern region due to the optical proximity effect is prevented. Further, according to the present invention, when the coding implantation is being performed on the pre-coding memory cells in the memory cell region, the threshold voltage of the transistors in the periphery circuit region is being adjusted concurrently to further simplify the manufacturing process.
Further, the present invention employs a photoresist layer as a patterned transferred layer. When the pattern-transferred layer comprises a photoresist material, a deposition step and an etching step can be omitted to further simplify the manufacturing procedure and to further reduce the manufacturing cost. Moreover, the present invention simply employs two layers of photoresist to improve any deviation in the critical dimension between the dense pattern region and the isolated pattern region.
Further, the first opening and the second opening of the mask layer can form with one piece of photomask or two pieces of photomask. The precise layer in the periphery circuit region can be completely opened or selectively opened or completely not opened.
The present invention provides a fabrication method for a read only memory device. The method provides a substrate that comprises a memory cell region and a periphery circuit region, wherein a memory cell array is already formed in the memory cell region and a plurality of transistors is formed in the periphery circuit region. A negative photoresist layer is then formed on the memory cell region, followed by performing a first exposure process to transfer the pattern of the first photomask to the first negative photoresist layer, wherein the pattern of the first photomask precisely correspondes to the channel region of each memory cell in the memory cell region. The non-crosslinked portion of the first photoresist layer is positioned above the channel region of each memory cell in the memory cell region. A second negative photoresist layer is then formed on the substrate. A second exposure process is performed to transfer the pattern of the second photomask to the second photoresist layer and to the first negative photoresist layer, wherein the pattern of the second photomask corresponds to a plurality of the pre-coding memory cell regions in the memory cell region and the gates of the transistors in the periphery circuit region. As a result, the non-crosslinked portions of the first negative photoresist layer and the second photoresist layer are positioned above the plurality of the pre-coding memory cell regions in the memory cell region and above the gates of the transistors in the periphery circuit region. A development process is conducted to pattern the first negative photoresist layer and the second photoresist layer. An ion implantation process is conducted to code the pre-coding memory cells in the pre-coding memory cell region and to adjust the threshold voltage of the transistors using the patterned first negative photoresist layer and the pattern second negative photoresist layer as a mask.
According to the present invention, after forming the first negative photoresist layer, the pattern of the precise photomask is transferred to the first negative photoresist layer, wherein the non-crosslinked portion of the first negative photoresist layer is located above the channel region of each memory cell. Thereafter, a second negative photoresist layer is formed. The pattern of the second photomask is then transferred to the first negative photoresist layer and the second negative photoresist layer. The opaque portion of the second photomask is positioned above the pre-coding memory cell region in the memory cell region and above the gates of the transistors in the periphery circuit region. Therefore, the non-crosslinked portions of the first negative photoresist layer and the second negative photoresist layer are positioned above the pre-coding memory cells in the pre-coding memory cell region. Moreover, the non-crosslinked portion of the second negative photoresist layer is also positioned above the gates of the transistors in the peripheral circuit region. After this, the non-crosslinked portions of the first negative photresist layer and the second photoresist layer are removed to form a plurality of openings in the memory cell region, wherein the critical dimension of these openings is identical. Further, these openings are located above the channel region of each pre-coding memory cell in the pre-coding memory cell region. Since the critical dimension of each opening above the channel region of the pre-coding memory cell in the pre-coding memory cell region is identical, any deviation in the critical dimension of the coding window between the dense pattern region and the isolated pattern region due to the optical proximity effect is prevented, even without the application of the optical proximity correction technique to manufacture the coding mask. Moreover, as the code implantation is being performed to the pre-coding memory cell in the memory cell region in the present invention, the threshold voltage of the transistors in the periphery circuit region is concurrently being adjusted to further simplify the manufacturing process.
Accordingly, the present invention sequentially performs two exposure processes on the two negative photoresist layers with two layers of the photomask and a single development process to pattern the two negative photoresist layers. The number of manufacturing steps in the present invention is greatly reduced to further reduce the manufacturing time and cost. Moreover, the two negative photoresist layers can be formed into a same photoresist layer. In summary, the present invention simply employs two photoresist layers to improve the deviation in the critical dimension of the coding window between the dense pattern region and the isolated pattern region due to the optical proximity effect.
The present invention further provides a fabrication method for a read only memory device. The method provides a substrate that comprises a memory cell region and a periphery circuit region, wherein a memory cell array is already formed in the memory cell region and a plurality of transistors is already formed in the periphery circuit region. A first negative photoresist layer is formed on the substrate, followed by performing a first exposure process to transfer the pattern in the first photomask to the first negative photoresist layer, wherein the pattern in the first photomask corresponds to a plurality of pre-coding memory cells and the gates of the transistors in the periphery circuit region. The non-crosslinked portion of the first negative photoreisist layer is positioned above a plurality of the pre-coding memory cell regions in the memory cell region and the gate of the transistors in the periphery circuit region. The pre-coding memory cell region further comprises the plurality of the pre-coding memory cells. Thereafter, a second negative photoresist layer is formed on the memory cell region. A second exposure process is performed to transfer the pattern of the second photomask to the first negative photoresist layer and the second negative photoresist layer, wherein the pattern in the second photomask precisely corresponds to the channel region of each memory cell in the memory cell region. The non-crosslinked portions of the second photoresist layer and the first photoresist layer are located above the channel region of each memory cell in the pre-coding memory cell region. A development process is performed to pattern the first negative photoresist layer and the second negative photoresist layer. Using the patterned first negative photoresist layer and the second negative photoresist layer as a mask, an ion implantation process is conducted to code the pre-coding memory cells in the pre-coding memory cell region and to adjust the threshold voltage of the transistors.
According to the present invention, subsequent to the formation of the first negative photoresist layer, the pattern of the first photomask is transferred to the first negative photoresist layer. The opaque portion of the first photomask is located above the pre-coding memory cell regions in the memory cell region and the gates of the transistors in the periphery region. Therefore, the non-crosslinked portion of the first negative photoresist layer in the memory cell region is located above the pre-coding memory cell regions and the gates of the transistors. Thereafter, a second negative photoresist layer is formed, followed by transferring the pattern of the second photomask (precise mask) to the first negative photoresist layer and to the second negative photoresist layer. The non-crosslinked portion of the first negative photoresist layer and the second negative photoresist layer are positioned above the channel region of each memory cell. After this, the non-crosslinked portions of the first negative photoresist layer and the second negative photoresist layer are removed to form a plurality of openings having identical critical dimension. These openings are positioned above the channel region of each memory cell in the pre-coding memory cell region, exposing the word line of the memory cell. Since the critical dimension of the openings above the channel region of each pre-coding memory cell is identical deviation in the critical dimension of the coding window between the dense pattern region and the isolated pattern region due to the optical proximity effect is prevented, even without the application of the optical proximity correction technique. Moreover, as code implantation is performed on the pre-coding memory cells in the memory cell region, the threshold voltage of the transistosr in the periphery circuit region is concurrently adjusted to further simplify the manufacturing process.
Accordingly, the present invention sequentially performs two exposure processes on the two negative photoresist layers with two layers of the photomask and a single development process to pattern the two negative photoresist layers. The number of manufacturing steps in the present invention is greatly reduced to further reduce the manufacturing time and cost. Moreover, the two negative photoresist layers can be formed into a same photoresist layer. In summary, the present invention simply employs two photoresist layers to improve the deviation in the critical dimension of the coding window between the dense pattern region and the isolated pattern region due to the optical proximity effect.
Although two photomasks are employed in the manufacturing of a read only memory, one of the photomasks is only required to expose the pre-coding memory cell region in the memory cell region and to concurrently expose the transistors in the periphery circuit region during the coding process. Therefore, this photomask does not have to be as precise as the conventional coding mask. The manufacturing cost for this photomask is thus lower. The other photomask in this embodiment is a precise mask, wherein the specification is uniform. Although the manufacturing cost for this photomask is higher, this photomask can be used repeatedly because the precise mask is only applicable for forming the openings having identical critical dimension in the channel region of the memory cell. Further, the conventional coding mask requires the optical proximity correction technique to mitigate the inaccuracy in pattern transference due to the optical proximity effect, the manufacturing cost for the conventional coding mask is thus very high. In the present invention, the pattern dimension in the dense pattern region and the pattern dimension in the isolated pattern region are identical, even without the application of a special patterned photomask formed with the optical proximity correction technique, the manufacturing cost is thus lower. Further, the advantages provided by the present invention can be accomplished whether the mask layer is formed before the precise layer or the precise layer is formed before the mask layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.